#project-update #rowhammerJanuary 3, 2022Open Source FPGA Platform for Rowhammer Security Testing in the Data Center
#tutorial #skywaterDecember 17, 2021Software-driven ASIC Prototyping Using the Open Source SkyWater Shuttle
#project-update #openlane #openroad #yosys #surelog #uhdm #swerv #ibex #core-v #blackparrot #opemtitan #risc-vOctober 27, 2021Improving the OpenLane ASIC Build Flow with Open Source SystemVerilog Support
#event-recap #risc-v #asic-design #fpga #omnixtendOctober 26, 2021Recap of the Fall 2021 CHIPS Alliance Workshop
#project-update #rowhammerSeptember 28, 2021Open Source DDR Controller Framework for Mitigating Rowhammer
#interview #risc-v #aib #systemverilog #verilatorSeptember 24, 2021Listen to CHIPS Alliance’s Rob Mains on EE Journal’s FishFry Podcast
#announcement #skywaterSeptember 16, 2021SkyWater Technology Joins CHIPS Alliance to Further Efforts to Make Chip Design and Production More Accessible
#project-update #f4pgaSeptember 9, 2021SymbiFlow FPGA Interchange Format to Enable Interoperable FPGA Tooling
#tutorial #verible #risc-vSeptember 8, 2021Automatic SystemVerilog Linting in GitHub Actions with Verible
