#project-update #openlane #openroad #yosys #surelog #uhdm #swerv #ibex #core-v #blackparrot #opemtitan #risc-v October 27, 2021 Improving the OpenLane ASIC Build Flow with Open Source SystemVerilog Support
#event-recap #risc-v #asic-design #fpga #omnixtend October 26, 2021 Recap of the Fall 2021 CHIPS Alliance Workshop
#project-update #rowhammer September 28, 2021 Open Source DDR Controller Framework for Mitigating Rowhammer
#interview #risc-v #aib #systemverilog #verilator September 24, 2021 Listen to CHIPS Alliance’s Rob Mains on EE Journal’s FishFry Podcast
#announcement #skywater September 16, 2021 SkyWater Technology Joins CHIPS Alliance to Further Efforts to Make Chip Design and Production More Accessible
#project-update #f4pga September 9, 2021 SymbiFlow FPGA Interchange Format to Enable Interoperable FPGA Tooling
#[tutorial verible risc-v] September 8, 2021 Automatic SystemVerilog Linting in GitHub Actions with Verible
#tutorial September 2, 2021 Open Source Custom GitHub Actions Runners with Google Cloud and Terraform
#project-update #systemverilog #tooling #verification August 4, 2021 Open Source SystemVerilog Tools in ASIC Design
#project-update #verilator July 20, 2021 Advanced Co-simulation with Renode and Verilator: PolarFire SoC and FastVDMA
