#project-update #verilator #risc-v May 13, 2021 Dynamic Scheduling in Verilator – Milestone Towards Open Source UVM
#announcement #mpw #skywater #openlane #openroad April 29, 2021 New MPW-TWO Program Will Provide Fabrication For Fully Open Source Projects
#project-update #fpga #lpddr4 #litedram #rowhammer April 9, 2021 Modular, Open-source FPGA-based LPDDR4 Test Platform
#announcement #omnixtend March 24, 2021 CHIPS Alliance and RISC-V International Invite the RISC-V Community to Participate in Updating a New Unified Memory Architecture Standard
#tutorial #github-actions #openroad #symbiflow #risc-v March 16, 2021 GitHub Actions Self-hosted Runners, Build Event Server and Google Cloud
#project-update #fusesoc #swervolf #serv #verilator #symbiflow #openroad #yosys #risc-v February 23, 2021 Goings-on in the FuseSoC Project and Other Open Source Silicon Related News
#announcement #risc-v February 11, 2021 CHIPS Alliance Welcomes Antmicro and VeriSilicon to the Platinum Membership Level
#project-update #pcie #litex #risc-v February 11, 2021 High-Throughput Open Source PCIe on Xilinx VU19P-Based ASIC Prototyping Platform
#project-update #yosys #verilator #uhdm #surelog #ibex #risc-v #opentitan January 7, 2021 Enabling Open Source Ibex Synthesis and Simulation in Verilator/Yosys via UHDM/Surelog
#announcement #openroad #yosys #f4pga December 15, 2020 Efabless Joins CHIPS Alliance to Accelerate the Growth of the Open Source Chip Ecosystem
