#announcement September 15, 2020 The CHIPS Alliance Workshop: 10 Talks From Industry Leaders, All For Free
#announcement #fpga August 11, 2020 QuickLogic Joins CHIPS Alliance to Expand Open Source FPGA Efforts
#release-notes #announcement July 16, 2020 CHIPS Alliance Announces AIB 2.0 Draft Specification to Accelerate Design of Open Source Chiplets
#project-update #risc-v #verilator #swerv July 10, 2020 CHIPS SweRV Cores and the Open Tools Ecosystem
#project-update #pdk #skywater June 29, 2020 Open Source Process Design Kit from Google, SkyWater Technologies and Partners Released
#announcement #report #risc-v #aib June 8, 2020 A Look Back at the CHIPS Alliance’s Incredible Growth
#announcement #swerv #risc-v May 14, 2020 CHIPS Alliance’s Newly Enhanced SweRV Cores Available to All for Free
#tutorial #verilog May 7, 2020 SystemVerilog Linting and Formatting with FuseSoC – Verible Integration
#project-update #systemverilog #verible #language-server-protocol #lsp #asic-design January 22, 2020 Intel joins CHIPS Alliance to promote Advanced Interface Bus (AIB) as an open standard
