Enhanced System Verilog Support for Yosys via Antmicro plug-in

  • June 30, 2022

  • 1 minutes

  • 78 words


CHIPS Alliance is pleased to see the announcement by Antmicro for its development and contribution to the open source hardware community to provide a easy to use plug-in for any version of Yosys to allow import of System Verilog based designs. This development is made possible by the underlying utilization of the Unified Hardware Data Model (UHDM), a key open source data representation upon which EDA applications can be built. Details can be seen here from Antmicro: https://antmicro.com/blog/2022/02/simplifying-open-source-sv-synthesis-with-the-yosys-uhdm-plugin/