CHIPS Alliance to Collaborate with RISC-V to Standardize an Open Unified Memory Leveraging OmniXtend
CHIPS Alliance to highlight OmniXtend advances at RISC-V Summit
SAN FRANCISCO, Dec. 8, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that the organization will highlight OmniXtend advances in a presentation at the RISC-V Summit, taking place virtually from Dec. 8-10, 2020. The CHIPS Alliance plans to work with RISC-V International to standardize an open unified memory coherency bus leveraging OmniXtend to foster innovation for data-centric applications.
“As RISC-V is increasingly being considered for high end data center and enterprise applications, there is a need for seamless cache-coherent sharing memory systems,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance, and senior director of next-generation platforms architecture at Western Digital. “CHIPS Alliance is cooperating with RISC-V to standardize on a unified memory fabric and leverage OmniXtend, which allows heterogenous systems that use TileLink cache-coherence protocol to share the memory coherently. We see a unique opportunity because RISC-V is freely open, while other architectures don’t open up the coherency bus, with RISC-V we can create an open unified memory standard to accelerate innovation for data-centric, heterogeneous applications.”
Said Mark Himelstein, CTO at RISC-V International: “ISAs do not stand alone. RISC-V needs a robust ecosystem and the OmniXtend roadmap will enable RISC-V members to create systems that deliver coherent, robust and performant solutions spanning the memory and storage hierarchies.”
Dr. Bandić will be presenting the session “OmniXtend: Open Source Cache-coherence over Ethernet” on Wednesday, Dec. 9 at 12:30 p.m. PT. The session will discuss OmniXtend, a cache-coherency protocol architecture that exports Tilelink cache-coherence messages on the top of L2 ethernet frames. The presentation will report the results of four RISC-V nodes, each running four independent RISC-V harts, connecting via commercial ethernet switch, and establishing a ccNUMA (cache coherent non-uniform memory access) architecture. The session will also highlight a detailed study of local and non-local (i.e. going through ethernet switch) cache access latencies, and propose several software models for OmniXtend-backed architectures.
Omnixtend will also be discussed in another session at the RISC-V Summit, “Building Cache-coherent Scaleout Systems with Omnixtend” with Atish Patra and Tu Dang at Western Digital on Tuesday, Dec. 8 at 3:30 p.m. PT. Atish and Tu will discuss how to provide the necessary support for OmniXtend to build a scalable system with thousands of nodes, since designing, verifying and deploying these scale-out systems in hardware is time consuming. The session will cover a two-fold approach to build and accelerate the development of OmniXtend scale-out systems: an initialization and configuration protocol defining a simple yet race-free approach to setting up multiple OmniXtend nodes during boot, and a software simulation/emulation framework which implements the OmniXtend protocol and an Omnixtend system emulation using Qemu.
The RISC-V Summit will also feature a keynote about the open ecosystem of modern tools, frameworks and platforms that are creating a seamless environment for developers to build advanced ML applications on RISC-V. The session, “Building an Open Edge Machine Learning Ecosystem with RISC-V, Zephyr, TensorFlow Lite Micro and Renode,” will take place on Tuesday, Dec. 8 at 10 a.m. PT and will be moderated by Michael Gielda at Antmicro and feature Tim Ansell at Google, Kate Stewart at the Zephyr Project and Brian Faith at QuickLogic.
To learn more about the RISC-V Summit, please visit: https://tmt.knect365.com/risc-v-summit/.
To register for the RISC-V Summit, please visit: https://riscv.informatech.com/2020/registrations/Attendee.
About the CHIPS Alliance
The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.
About the Linux Foundation
The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.