F4PGA
Free and open source toolchain for FPGA devices
FPGA tool perf
Framework for automatic FPGA toolchains benchmarking
FPGA Interchange format
FPGA Interchange is a Vendor agnostic FPGA devices and designs description. It enables interoperability between different FPGA tools.
RocketChip
The SoC generator instantiates the RISC-V Rocket Core and relevant component.
Surelog and UHDM
SureLog is a SystemVerilog 2017 Pre-processor, Parser, UHDM Compiler providing IEEE Design/TB VPI and Python AST API. UHDM is the underlying Hardware Data Model framework. More info: https://woset-workshop.github.io/WOSET2020.html#article-10
SV tests
SystemVerilog test framework for checking SV spec support coverage in various open source tools - parsers, linters, formatters etc.
