Projects

Graduated Projects

Caliptra

The Caliptra project focuses on development of HW and SW IP for the Caliptra Root of Trust

Repositories:

RocketChip

The SoC generator instantiates the RISC-V Rocket Core and relevant component.

Repositories:

rocket-chip

Surelog and UHDM

SureLog is a SystemVerilog 2017 Pre-processor, Parser, UHDM Compiler providing IEEE Design/TB VPI and Python AST API. UHDM is the underlying Hardware Data Model framework. More info: https://woset-workshop.github.io/WOSET2020.html#article-10

Repositories:

SV tests

SystemVerilog test framework for checking SV spec support coverage in various open source tools - parsers, linters, formatters etc.

Repositories:

sv-tests

Intel Compiler for SystemC

Open source SystemC to SystemVerilog translation tool and SingleSource library.

Repositories:

systemc-compiler

Verible

Parse SystemVerilog (IEEE 1800-2017) with a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

Repositories:

verible

F4PGA

Free and open source toolchain for FPGA devices

Repositories:

f4pga

FPGA Interchange format

FPGA Interchange is a Vendor agnostic FPGA devices and designs description. It enables interoperability between different FPGA tools.

Repositories:

fpga-interchange-schema

FPGA tool perf

Framework for automatic FPGA toolchains benchmarking

Repositories:

RISCV-DV

RISCV-DV is an open source verification tool for RISC-V processors. RISCV-DV is a SystemVerilog based random RISC-V instruction generator that checks the execution against an industry standard ISS for correction and compliance.

Repositories:

riscv-dv

Sandbox Projects

Chisel

Support the Chisel Hardware Construction Language and related projects

Repositories:

chisel