CHIPS Alliance hosts many open source projects at various stages of their maturity lifecycle.


Graduated Projects


The Caliptra project focuses on development of HW and SW IP for the Caliptra Root of Trust


The SoC generator instantiates the RISC-V Rocket Core and relevant component.

Surelog and UHDM

SureLog is a SystemVerilog 2017 Pre-processor, Parser, UHDM Compiler providing IEEE Design/TB VPI and Python AST API. UHDM is the underlying Hardware Data Model framework. More info:

SV tests

SystemVerilog test framework for checking SV spec support coverage in various open source tools - parsers, linters, formatters etc.

Intel Compiler for SystemC

Open source SystemC to SystemVerilog translation tool and SingleSource library.


Parse SystemVerilog (IEEE 1800-2017) with a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server


Free and open source toolchain for FPGA devices

FPGA Interchange format

FPGA Interchange is a Vendor agnostic FPGA devices and designs description. It enables interoperability between different FPGA tools.

FPGA tool perf

Framework for automatic FPGA toolchains benchmarking


RISCV-DV is an open source verification tool for RISC-V processors. RISCV-DV is a SystemVerilog based random RISC-V instruction generator that checks the execution against an industry standard ISS for correction and compliance.

Sandbox Projects