Caliptra
The Caliptra project focuses on development of HW and SW IP for the Caliptra Root of Trust
Chisel
Support the Chisel Hardware Construction Language and related projects
- Repositories:
- Issue Tracker Website
- Contact: Jack Koenig (GitHub)
F4PGA
Free and open source toolchain for FPGA devices
- Repositories:
- Issue Tracker Website
- Contact: Tomasz Michalak (GitHub)
FPGA Interchange format
FPGA Interchange is a Vendor agnostic FPGA devices and designs description. It enables interoperability between different FPGA tools.
- Repositories:
- Issue Tracker Website
- Contact: Maciej Kurc (GitHub)
FPGA tool perf
Framework for automatic FPGA toolchains benchmarking
- Repositories:
- Issue Tracker Website
- Contact: Tomasz Gorochowik (GitHub)
Intel Compiler for SystemC
Open source SystemC to SystemVerilog translation tool and SingleSource library.
- Repositories:
- Issue Tracker Website
- Contact: Mikhail Moiseev (GitHub)
OmniXtend
Cache coherence framework for RISC-V based on TileLink
OpenFASOC
Fully Open Source Automated Analog Block Generation built on top of OpenROAD, Magic, Netgen, Klayout and Ngspice
- Repositories:
- Issue Tracker Website
- Contact: Mehdi Saligane (GitHub)
RISCV-DV
RISCV-DV is an open source verification tool for RISC-V processors. RISCV-DV is a SystemVerilog based random RISC-V instruction generator that checks the execution against an industry standard ISS for correction and compliance.
- Repositories:
- Issue Tracker Website
- Contact: Matt Cockrell (GitHub)
RocketChip
The SoC generator instantiates the RISC-V Rocket Core and relevant component.
- Repositories:
- Issue Tracker Website
- Contact: Jiuyang Liu (GitHub)
Surelog and UHDM
SureLog is a SystemVerilog 2017 Pre-processor, Parser, UHDM Compiler providing IEEE Design/TB VPI and Python AST API. UHDM is the underlying Hardware Data Model framework. More info: https://woset-workshop.github.io/WOSET2020.html#article-10
- Repositories:
- Issue Tracker Website
- Contact: Alain Dargelas (GitHub)
SV tests
SystemVerilog test framework for checking SV spec support coverage in various open source tools - parsers, linters, formatters etc.
- Repositories:
- Issue Tracker Website
- Contact: Tom Gorochowik (GitHub)
VeeR
RTL designs for the VeeR (Very Efficient & Elegant RISC-V) cores (EH1, EH2, EL2).
Verible
Parse SystemVerilog (IEEE 1800-2017) with a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
- Repositories:
- Issue Tracker Website
- Contact: Henner Zeller (GitHub)