#project-update #f4pga October 9, 2022 F4PGA open source flow gets a new Python-based build system and CLI tool
#project-update #verilator #uvm February 1, 2022 Towards UVM: Using Coroutines for Low-overhead Dynamic Scheduling in Verilator
#project-update #rowhammer January 3, 2022 Open Source FPGA Platform for Rowhammer Security Testing in the Data Center
#project-update #openlane #openroad #yosys #surelog #uhdm #swerv #ibex #core-v #blackparrot #opemtitan #risc-v October 27, 2021 Improving the OpenLane ASIC Build Flow with Open Source SystemVerilog Support
#project-update #rowhammer September 28, 2021 Open Source DDR Controller Framework for Mitigating Rowhammer
#project-update #f4pga September 9, 2021 SymbiFlow FPGA Interchange Format to Enable Interoperable FPGA Tooling
#project-update #systemverilog #tooling #verification August 4, 2021 Open Source SystemVerilog Tools in ASIC Design
