#project-update #verilator July 20, 2021 Advanced Co-simulation with Renode and Verilator: PolarFire SoC and FastVDMA
#project-update #systemverilog #verible #yosys #verilator #uhdm #surelog July 20, 2021 Progress on Building Open Source Infrastructure for System Verilog
#project-update #verilator #risc-v May 13, 2021 Dynamic Scheduling in Verilator – Milestone Towards Open Source UVM
#project-update #fpga #lpddr4 #litedram #rowhammer April 9, 2021 Modular, Open-source FPGA-based LPDDR4 Test Platform
#project-update #fusesoc #swervolf #serv #verilator #symbiflow #openroad #yosys #risc-v February 23, 2021 Goings-on in the FuseSoC Project and Other Open Source Silicon Related News
#project-update #pcie #litex #risc-v February 11, 2021 High-Throughput Open Source PCIe on Xilinx VU19P-Based ASIC Prototyping Platform
#project-update #yosys #verilator #uhdm #surelog #ibex #risc-v #opentitan January 7, 2021 Enabling Open Source Ibex Synthesis and Simulation in Verilator/Yosys via UHDM/Surelog
#project-update #risc-v #verilator #swerv July 10, 2020 CHIPS SweRV Cores and the Open Tools Ecosystem
#project-update #pdk #skywater June 29, 2020 Open Source Process Design Kit from Google, SkyWater Technologies and Partners Released
#project-update #systemverilog #verible #language-server-protocol #lsp #asic-design January 22, 2020 Intel joins CHIPS Alliance to promote Advanced Interface Bus (AIB) as an open standard
