#announcement #risc-v February 11, 2021 CHIPS Alliance Welcomes Antmicro and VeriSilicon to the Platinum Membership Level
#project-update #pcie #litex #risc-v February 11, 2021 High-Throughput Open Source PCIe on Xilinx VU19P-Based ASIC Prototyping Platform
#project-update #yosys #verilator #uhdm #surelog #ibex #risc-v #opentitan January 7, 2021 Enabling Open Source Ibex Synthesis and Simulation in Verilator/Yosys via UHDM/Surelog
#project-update #risc-v #verilator #swerv July 10, 2020 CHIPS SweRV Cores and the Open Tools Ecosystem
#announcement #report #risc-v #aib June 8, 2020 A Look Back at the CHIPS Alliance’s Incredible Growth
#announcement #swerv #risc-v May 14, 2020 CHIPS Alliance’s Newly Enhanced SweRV Cores Available to All for Free
#announcement #chisel #verilator #risc-v November 7, 2019 CHIPS Alliance announces technical milestones, three new workgroups including Chisel and the 3rd Chisel Community Conference
#announcement #risc-v October 15, 2019 CHIPS Alliance growth continues with new members and design workshop this November
#announcement #risc-v June 18, 2019 CHIPS Alliance Builds Momentum and Community with Newest Members Imperas Software and Metrics
#announcement #roadmap #risc-v #verilator #chisel May 7, 2019 CHIPS Alliance to Reveal Project Details, Strategy and Roadmap at Inaugural Workshop Hosted at Google
