#project-update #fusesoc #swervolf #serv #verilator #symbiflow #openroad #yosys #risc-v February 23, 2021 Goings-on in the FuseSoC Project and Other Open Source Silicon Related News
#project-update #yosys #verilator #uhdm #surelog #ibex #risc-v #opentitan January 7, 2021 Enabling Open Source Ibex Synthesis and Simulation in Verilator/Yosys via UHDM/Surelog
#project-update #risc-v #verilator #swerv July 10, 2020 CHIPS SweRV Cores and the Open Tools Ecosystem
#announcement #chisel #verilator #risc-v November 7, 2019 CHIPS Alliance announces technical milestones, three new workgroups including Chisel and the 3rd Chisel Community Conference
#announcement #roadmap #risc-v #verilator #chisel May 7, 2019 CHIPS Alliance to Reveal Project Details, Strategy and Roadmap at Inaugural Workshop Hosted at Google
