CHIPS Alliance will be adding Projects over time as the community gets started and may spin up or wind down Workgroups as needed to reflect our work across the SoC and tooling ecosystem. We welcome code, engineer involvement and partnership collaborations to further define and focus projects into relevant and strategically critical opportunities. Members and non-members alike are invited to participate in our work to change the landscape of chip development to be more open source. Please join the technical-discuss mailing list to get started!
The Analog workgroup was formed by the CHIPS Alliance TSC to explore collaborations in open source Analog/Mixed-Signal design and verification. It focuses on sharing best practices, ideas, tooling (analog automation), and other challenge areas in the design space. The workgroup is composed of both industry and university members.
- Leader: Mehdi Saligane (@msaligane)
- Mailing List: email@example.com
- Meeting Dates: Every Tuesday at 9:00 a.m. PT as scheduled
- Meeting Link: https://zoom.us/j/93893684803 (passcode: analog)
- Website: https://github.com/chipsalliance/Caliptra
- Leader: Bharat Pillilli
- Mailing List: https://lists.chipsalliance.org/g/caliptra-wg
- Meeting Dates: Every Friday 9am PST
The Chisel Workgroup is formed around the eponymous hardware design language (HDL) that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog. Chisel is powered by FIRRTL (Flexible Intermediate Representation for RTL), a hardware compiler framework that performs optimizations of Chisel-generated circuits and supports custom user-defined circuit transformations on an Intermediate Representation. The WG also covers tools such as Treadle which is an experimental circuit simulator that executes the Firrtl IR.
- Website: https://www.chisel-lang.org/
- Leader: Jack Koenig (@jackkoenig)
- Mailing List: https://lists.chipsalliance.org/g/chisel-wg/topics
The F4PGA Workgroup was formed to drive open source tooling, IP cores and research for FPGA devices. It includes three major groups whose collaboration is critical to the success of the open source approach in this space: FPGA vendors, industrial users and university members. Its main focus is enabling rapid prototyping and software-driven development of FPGA-oriented systems in areas such as ML and video processing. The workgroup provides an open collaboration platform for its members, aiming at accelerating the speed of innovation in FPGAs and the general availability of the technology. The initial projects contributed into CHIPS Alliance within the F4PGA Workgroup are focused around the free and open source FPGA toolchain formerly known as SymbiFlow, as well as the so-called FPGA Interchange format.
- Website: https://f4pga.org/
- Leader: Tomasz Michalak (@tmichalak)
- Mailing List: https://lists.chipsalliance.org/g/f4pga-wg
The Rocket Chip Workgroup covers the “Rocket” pipelined implementation of a RISC-V core as well as a TileLink uncore and cache coherent memory hierarchy. The main rocket-chip repository that the group maintains is a meta-repository containing tools needed to generate and test RTL implementations of SoC designs. This repository contains code that is used to generate RTL using Chisel and Diplomacy: the Rocket Chip generator itself is a Scala program that invokes the Diplomacy library and Chisel compiler in order to emit RTL describing a complete SoC.
- Leader: Jiuyang Liu (@sequencer)
- Mailing List: https://lists.chipsalliance.org/g/rocket-wg
The Tools workgroup (WG) of CHIPS Alliance covers a wide array of open source tooling for ASIC and FPGA design, mostly focusing around digital design (as there is a separate Analog WG that focuses on AMS design flows). The topics covered include simulation, synthesis, place and route, IP aggregation, linting, formatting, and many more.
- Leader: Karol Gugala (@kgugala)
- Mailing List: https://lists.chipsalliance.org/g/tools-wg
- Meeting Dates: Every other Friday (currently even weeks) at 7 a.m. PT
- Meeting Link: https://meet.google.com/ncy-rzzp-tfv?hs=122